Synthesizable IP Sales
Through our partnership with HDL Design House, Epiphyte is able to offer the following IP cores for sale:
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Reed Solomon CODEC IP Core
Solomon codes, a class of error correction codes, are block-oriented coding schemes used in communication systems for FEC (Forward Error Correction). Information coding prior to transmission is performed against limited transmit power/bandwidth. ReedSolomon decoding architectures contribute to systems that are sensitive to transmission errors, with no data acknowledge or data retransmit. They are well suited for correcting errors that occur in bursts. Combined with a Viterbi coding scheme, ReedSolomon codes can be used to create concatenated code with increased performance.
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I2S Soft IP core (HIP 3700)
I2S is an audio transmission standard, used to connect system elements such as Analog to Digital and Digital to Analog converters, speakers or audio subsystems. HIP 3700 is silicon proven I2S Controller IP Core compliant to the Philips* Inter-IC Sound specification. IP Core provides up to 8 audio channels and a 32-bit parallel processor bus as the application interface. Each channel can be programmed as an I2S master or an I2S slave.
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Serial RapidIO Soft IP Core (HIP 3300)
Serial RapidIO is a data communication standard provisioned for the interconnection of devices on the same circuit board or between circuit boards across a backplane. It has been developed as a more cost-effective, standards, switched based replacement for expensive proprietary buses in high-performance embedded systems, such as networking and communications equipment and enterprise storage.
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SPI flash memory controller (HIP 3100
SPI flash memory controller allows flexible, fast and high performance implementation of an AHB subsystem having SPI flash memories and offloading AHB master from direct control of SPI flash memories and executes SPI data operations. It supports up to 16 flash memory devices of any memory size organized in up to 4 memory clusters. AHB master configures SPI controller, provides necessary data (in the case of memory write operation) or read data (in the case of memory read operation) and starts SPI controller. SPI controller can decode and execute SPI flash memory instructions controlling directly SPI flash memories and offload AHB master from this task.
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PSPP1284 IEEE 1284 Parallel Port Controller (IEEE 1284)
The PSPP1284 core implements the IEEE 1284 interface. Software-programmable for the operation as a host or peripheral device, the core supports Compatible, Nibble, Byte, EPP, and ECP mode of operations and includes a configurable depth FIFO tightly coupled with the DMA engine for efficient data transfer in ECP mode. Full-speed data transfer can be performed by initializing the core in ECP operation mode with DMA transfer enabled, and waiting for an interrupt at completion. The core provides a solution for parallel ports that requires minimal software assistance.
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HCR_DES_TDES Crypto Core Family (HIP 1100)
The HCR_DES_TDES crypto core family is group of high-performance crypto cores that implement the NIST FIPS PUB 46-3 algorithm in hardware. This family of IP crypto cores can be used to enable integration in today’s SoC designs.
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HCR_AES Crypto Core Family (HIP1000)
The HCR_AES crypto core family is high-performance family of cores that allow the implementation of the NIST FIPS PUB 197 algorithm in hardware. These cores can be integrated into SoC designs.